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NXP bidirectional low-voltage translators GTL20xx
Low cost bidirectional voltage Headline translation without directional control
Unlikelevel-shiftingbusswitches,whichonlytranslatebetweenfixedvoltages,thesebidirectional low-voltagetranslatorscantranslateanyvoltagebetween1and5Vtoanyothervoltagebetween 1and5V.TheyalsoreduceON-stateresistanceandminimizepropagationdelay.
Key features 4 odirectionalcontrolrequiredfor N bidirectionalvoltagetranslations 4 owRONresistance(6.5)between L inputandoutputpins(Sn/Dn) 4 ropagationdelay:1.5ns(typ) P 4 hanneloff-statecapacitance:7.5pF C 4 erylow(5A)standbycurrent V 4 opowersupplyrequired-prevents N latch-ups 4 erysmallQFNpackageoptions V Applications 4 ni-andbidirectionaltranslationfor U anyvoltagebetween1and5V 4 idirectionaltranslationoflowB voltageandlegacyI2C-bussignals 4 hiftingprocessorsidebandI/O S signalsbetweenGTLandLVTTL/TTL levels TheNXPfamilyofGunningTransceiver Logic(GTL)bidirectionallow-voltage translatorsincludesthe22-bitGTL2000, the2-bitGTL2002,the8-bitGTL2003, andthe10-bitGTL2010. Eachdelivershigh-speedtranslation betweendifferentvoltagelevelswith lowON-stateresistanceandminimal propagationdelay. Theycantranslateanyvoltagebetween 1and5Vtoanyothervoltagebetween 1and5Vaslongasthereisatleast1V differencebetweenthevoltagelevels,so theyoffergreaterdesignflexibilitythan level-shiftingbusswitches,whichonly translatebetweenfixedvoltages. EachGTL20xxdeviceincludesNMOS passtransistors(SnandDnpins)witha commongate(GREFpin)andareference transistor(SREFandDREFpins). WhenoneoftheSnorDnportsislow, theclampisintheON-stateandtheSn andDnportsarelinkedthroughalow ON-resistanceconnection.Assumingthe highervoltageisappliedontheDnport, whentheDnportishigh,thevoltageon theSnportislimitedtothevoltageset bySREF.WhentheSnportishigh,theDn portispulledtoahighervoltagebya pull-upresistor. Thisset-upenablesseamlesstranslation betweenuser-selectedvoltages,without theneedfordirectionalcontrolsignals. Alltransistorshavethesameelectrical characteristicssodeviationfromone outputtoanotherinvoltageand propagationdelayiskepttoaminimum. Thetransistorsalsoprovideexcellent ESDprotectionincasethelow-voltage devicesthatarelessresistanttoESD. Thetranslatorscanbeusedinany
applicationthatrequiresuni-or bidirectionalvoltagetranslationfor voltagelevelsbetween1and5V. Theopen-drainconstruction,which eliminatestheneedfordirectional control,makesthetranslatorsidealfor designsthatcombinelow-voltage(1.0to 1.8V)andlegacy(3.3and/or5.5V)I2Cbussignals.Thetranslatorscanchange I2C-bussignallevelsatspeedsupto3.4 MHz. Thetranslatorscanalsobeusedin designsthatcombineGTLandLVTTL/ TTLsignals,shiftingprocessorsideband I/Osignalsbetweenvoltagelevels. Bidirectional voltage translation Toconfigurethetranslatorsfor bidirectionalclamping,theGREFinput mustbeconnectedtoDREFandboth pinsmustbepulledtothehigh-side VCCthroughapull-upresistor(typically 200k).AfiltercapacitoronDREFis recommended. TheCPUoutputcanbesetastotem poleoropendrain(pull-upresistorsmay berequired),ascanthechipsetoutput (pull-upresistorsarerequiredtopull theDnoutputstoVCC).Nodirectional controlisneededifbothoutputsareset asopendrain.Ifeitheroutputissetto totempole,however,theremaybehighto-lowcontentionsineitherdirection.To preventthis,setdataasunidirectional oruse3-stateableoutputswitha mechanismfordirectioncontrol. TheoppositesideofSREFisconnected totheCPUpower-supplyvoltage.When DREFisconnectedthrougha200-k resistortoVCCandSREFissetbetween1.0 andVCCminus1.5V,theoutputofeach Snhasamaximumoutputvoltageequal
toSREFandtheoutputofeachDnhasa maximumoutputvoltageequaltothe voltageofthepull-upresistor(3.3and/or 5V). Unidirectional voltage translation Thesameconfigurationcanbeusedfor one-wayvoltagetranslation,eitherup ordown.Fordown-onlytranslation,if thechipsetI/Oareopendrain,pull-up resistorsarerequired.
Forup-onlytranslation,apull-upresistor isrequiredonthehigh-sidevoltage(Dn). Thisisbecausethetranslatorwillonly passthereferencesourcevoltage(SREF) asahighwhendoingup-translation.The driveronthelow-sidevoltageonlyneeds apull-upresistorifitissetasopendrain. Formoreinformationonusingthe GTL20xxfamily,pleasereferto ApplicationNoteAN10145atwww.nxp. com/interface.
GND SREF S1 S2 S3 S4 S5 S6 S7
1 2 3 4 5 6 7 8 9
48 47 46 45 44 43 42 41 40 39
GREF DREF D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22
S4 S5 Sn D4 D5 Dn S3 D3 Increase bit size by using 8-bit GTL2003 or 10-bit GTL2010 or 22-bit GTL2000 3.3 V VCORE S REF S1 CPU I/O S2 D2
GTL2002
GTL2003
1.8 V 1.5 V 1.2 V 1.0 V GND GREF D REF D1 Chipset I/O VCC GTL2002 5V Totem Pole or Open Drain I/O
GTL2010
200 K
S8 10 S9 11 S10 12 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 13 14 15 16 17 18 19 20 21 22 23
GTL2000
38 37 36 35 34 33 32 31 30 29 28 27 26 25
VCC
Chipset I/O
S22 24
GTL20xx pinout diagram
Typical configuration for bidirectional voltage translation
Ordering information
Package SO SSOP TSSOP HVQFN DHVQFN VSSOP XQFN Container Tube T&R Tube T&R Tube T&R T&R T&R T&R T&R GTL2000 --GTL2000DL GTL2000DL-T GTL2000DGG GTL2000DGG-T ----GTL2002 GTL2002D GTL2002D-T ---GTL2002DP-T --GTL2002DC-T GTL2002GM-T GTL2003 ----GTL2003PW GTL2003PW-T -GTL2003BQ-T --GTL2010 ----GTL2010PW GTL2010PW-T GTL2010BS-T ----
Note: In Europe and Asia, for tube orders, add ", 112" (e.g. GTL2010PW, 112), and for tape and reel orders, replace "-T" with ", 118" (e.g. GTL2010PW, 118).
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(c) 2007 NXP N.V. All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Date of release: March 2007 Document order number: 9397 750 15911 Printed in the USA

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